The present invention relates to a semiconductor memory and, more particularly, to a dynamic random access memory cell having a vertical transistor which is suitable for achieving high integration.
Japanese Patent Laid-Open No. 62-140456 (1985) discloses a dynamic random access memory wherein a memory cell comprising a vertical MIS transistor and a capacitor device is formed on a silicon island.
FIG. 1 is a sectional view showing the above-described conventional semiconductor memory. The dynamic random access memory of FIG. 1 includes a vertical MIS transistor which includes a p-type silicon island 22 formed on a p-type silicon substrate 21, a highly doped n-type impurity diffused layer 16, a word line 17 which operates as a gate electrode, a gate insulator 7, and a highly doped n-type impurity diffused layer 12. A charge-storage device includes the highly doped n-type impurity diffused layer 12, a capacitor insulator 3, and a plate electrode 13.
In the FIG. 1 prior art, the silicon island 22 that is employed to form a dynamic random access memory cell is electrically connected directly with the silicon substrate 21. There is a strong possibility that the charge stored in the cell will be reduced or destroyed, i.e., soft-error will occur. That is, positive or negative charges which are generated in the silicon substrate 21 along the track of any alpha particles passing through the silicon substrate into the island will gather in the highly doped n-type impurity diffused layer 12 of the capacitor.
Further, in the prior art no consideration is given to formation of a very small memory cell.